| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| artnetv3 [2016/09/24 17:25] – [Table] maxi2 | artnetv3 [2016/09/24 20:32] (current) – [Table] maxi2 |
|---|
| ====== ArtNET Node v3 ====== | ====== ArtNET Node v3 ====== |
| |
| ==== Registermap ==== | ===== FPGA Register ===== |
| | Der FPGA enthält ein paar Register, die über den SPI Bus von einem Microcontroller geschrieben/gelesen werden können. Mithilfe dieser Register werden alle Blöcke, die implementiert wurden, konfiguriert. |
| |
| ^ Address ^ Name ^ Description ^ Bit 7 ^ Bit 6 ^ Bit 5 ^ Bit 4 ^ Bit 3 ^ Bit 2 ^ Bit 1 ^ Bit 0 ^ | ==== SPI Kommunikation ==== |
| | 0x00 | IPADDR0 | Lowest byte of IP address | interpreted as byte |||||||| | |
| | 0x01 | IPADDR0 | ... | interpreted as byte |||||||| | === Register Schreiben === |
| | 0x02 | IPADDR2 | ... | interpreted as byte |||||||| | |
| | 0x03 | IPADDR3 | Highest byte of IP address | interpreted as byte |||||||| | Um ein Register zu schreiben muss zuerst der **Opcode 'w' (0x77)** gesendet werden, dann die **Registeradresse** und zu Letzt der neue **Wert**. |
| | | | | |||||||| | |
| | 0x0C | IOACFG | config of physical I/O A | X | X | X | direction\\ 0 = out, 1 = in | enable\\ 0 = disabled, 1 = enabled | address of data buffer ||| | {{:artnet_fpga_write_reg.png}} |
| | 0x0C | IOBCFG | config of physical I/O B | X | X | X | direction | enable | address of data buffer ||| | |
| | 0x0C | IOCCFG | config of physical I/O C | X | X | X | direction | enable | address of data buffer ||| | //Beispiel: Register 0x0B wird mit 0xB0 beschrieben// |
| | 0x0C | IODCFG | config of physical I/O D | X | X | X | direction | enable | address of data buffer ||| | |
| | 0x0C | IOECFG | config of physical I/O E | X | X | X | direction | enable | address of data buffer ||| | ==== Registermap ==== |
| | 0x0C | IOFCFG | config of physical I/O F | X | X | X | direction | enable | address of data buffer ||| | ^ Address ^ Name ^ Description ^ Bit 7 ^ Bit 6 ^ Bit 5 ^ Bit 4 ^ Bit 3 ^ Bit 2 ^ Bit 1 ^ Bit 0 ^ |
| | 0x0C | IOGCFG | config of physical I/O G | X | X | X | direction | enable | address of data buffer ||| | | 0x00 | IPADDR0 | Lowest byte of IP address | interpreted as byte |||||||| |
| | 0x0C | IOHCFG | config of physical I/O H | X | X | X | direction | enable | address of data buffer ||| | | 0x01 | IPADDR0 | ... | interpreted as byte |||||||| |
| | | 0x02 | IPADDR2 | ... | interpreted as byte |||||||| |
| | | 0x03 | IPADDR3 | Highest byte of IP address | interpreted as byte |||||||| |
| | | 0x04 | BUF0ADDR | ArtNET address buffer 0 | Sub-Net |||| Universe |||| |
| | | 0x05 | BUF1ADDR | ArtNET address buffer 1 | Sub-Net |||| Universe |||| |
| | | 0x06 | BUF2ADDR | ArtNET address buffer 2 | Sub-Net |||| Universe |||| |
| | | 0x07 | BUF3ADDR | ArtNET address buffer 3 | Sub-Net |||| Universe |||| |
| | | 0x08 | BUF4ADDR | ArtNET address buffer 4 | Sub-Net |||| Universe |||| |
| | | 0x09 | BUF5ADDR | ArtNET address buffer 5 | Sub-Net |||| Universe |||| |
| | | 0x0A | BUF6ADDR | ArtNET address buffer 6 | Sub-Net |||| Universe |||| |
| | | 0x0B | BUF7ADDR | ArtNET address buffer 7 | Sub-Net |||| Universe |||| |
| | | 0x0C | IOACFG | config of physical I/O A | X | X | X | direction\\ 0 = out, 1 = in | enable | address of data buffer ||| |
| | | 0x0D | IOBCFG | config of physical I/O B | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x0E | IOCCFG | config of physical I/O C | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x0F | IODCFG | config of physical I/O D | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x10 | IOECFG | config of physical I/O E | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x11 | IOFCFG | config of physical I/O F | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x12 | IOGCFG | config of physical I/O G | X | X | X | direction | enable | address of data buffer ||| |
| | | 0x13 | IOHCFG | config of physical I/O H | X | X | X | direction | enable | address of data buffer ||| |
